A semiconductor device such as a semiconductor memory includes an output driver that outputs digital data outside a chip. The output driver outputs data DQ as well as a strobe signal DQS which is a reference clock. At this time, when the drive capabilities (current drive capabilities) to pull up and down an output signal differ from each other, the timings at which the strobe signal DQS and the data DQ rise or fall are shifted from each other. By this, the data valid window decreases. Such a decrease in data valid window becomes a significant problem particularly in a semiconductor device that performs high-speed operation, such as a DRAM adopting DDR (Double Data Rate) Interface. To suppress a decrease in output data valid window, it is important for the output driver to make the drive capabilities to pull up and down an output signal equal to each other.
In addition, the slope (slew rate) of rise or fall of an output data waveform also affects the data valid window. For example, when the slew rate is low, the slope of rise or fall of output data is moderate and thus the output data valid window decreases. When the slew rate is high, the slope of rise or fall of output data is steep and thus the output data valid window does not decrease almost at all. Meanwhile, a sudden rise or fall of output data means sudden charge or discharge of a data bus and thus it may cause power supply noise, ringing, due to SSO (Simultaneous Switching Output) or reflection of an output signal, resulting in signal integrity degradation. Therefore, it is desirable that the output driver have a function to control slew rates in order to maintain a certain output data valid window suppressing power supply noise or reflection of an output signal.
Conventionally, to compose an output driver capable of adjusting the drive capability and the slew rate, a transistor Tr1 that receives a signal for enabling a sub-driver selectively, a transistor Tr2 that receives a signal for output data, and a transistor Tr3 that receives a signal for controlling the slew rate need to be connected in series. In order for the transistor Tr3 to dominantly control the slew rate, the current drive capabilities of other transistors Tr1 and Tr2 need to be sufficiently high with respect to the current drive capability of the transistor Tr3. Hence, the sizes of the transistors Tr1 and Tr2 need to be equal to or larger than the size of the transistor Tr3. In recent years, a reduction in power supply voltage of I/O circuits has been advanced and thus the current drive capabilities of transistors have inevitably decreased. Therefore, to maintain the current drive capabilities of transistors as high as possible, it is required to further increase the sizes of the transistors Tr1 to Tr3. However, if the sizes of the transistors Tr1 to Tr3 increase, then it becomes difficult to achieve a fine-line semiconductor device.